As the number of different applications for packet switching grows, the error monitoring and detection requirements have become more stringent on packet switching systems. Error recovery from a detected error in packet switching systems is handled by utilizing complex protocols. Such protocols are either implemented at the edges of a packet switching system or are implemented between each node within the system. In systems employing internode error recovery protocols, the nodes have generally been implemented by general purpose computers which have performed the packet switching functions utilizing sophisticated software packages. In addition, to performing the switching functions, the computers have also performed the error rate monitoring and error recovery protocols. Because of the real time constraints placed on the computer having to perform all of these functions, it is not feasible to implement algorithms for accurately measuring the error rate; instead, only algorithms which approximated the error rate on a particular transmission link are utilized.
In packet switching systems where the error recovery protocol is implemented at the edges of the system, it is only necessary to detect the occurrence of errors and to monitor the error rate between switching nodes. A packet switching system which implements the error recovery protocols at the edges of the system is disclosed in the above-identified applications. For example, the J. S. Turner, Case 8, Ser. No. 393112, "A Fast Packet Switching Network", describes a system comprising fast packet switching nodes interconnected by high speed digital transmission links with each link being terminated on both ends by an interface facility.
A communication path is setup through the fast packet switching system by initially routing a call setup packet from an originating terminal to each central processor controlling a switching node in the route to the destination terminal. That packet precedes all other packets for the message of the packet call. Each central processor is responsive to a receipt of the setup packet to store logical to physical address translation information in memories of its associated interface facilities. Thereafter, the central processor involvement in the communication of all subsequent packets for the message of that call is virtually eliminated. The physical address defines a path through the switching network of the switching node to an output interface facility in the communication path to the destination terminal.
Each interface facility utilizes its memory information for the assemblage of a new packet containing the physical address plus the originally received message packet. The interface facility then sends the new packet to the switching network. The switching network comprises switching elements which are responsive to the physical address in the new packet for establishing the physical path to the output interface facility.
Although the error recovery protocols are implemented at the edge of the fast packet switching system, it is necessary to perform error monitoring on each transmission link interconnecting the switching networks, and this monitoring should be performed in such a manner so as not to reduce the transmission capacity of the links. Since the associated processor does not handle each individual packet, there exists a need for techniques which would accurately perform the necessary monitoring functions. In addition, the monitoring should desirably introduce minimal additional delays into the switching of packets.